1. Field of the Invention
The present invention relates to an optical lithographic technology for forming microstructured patterns, more particularly to a method for exposing a light thereby to manufacture semiconductor devices.
2. Description of Related Art
In order to integrate semiconductor memories and microprocessors and speed up their operations more significantly, it will be unavoidable that the structure of the ULSI used for each of those devices must be formed precisely more and more. The most important item for such microstructure of an ULSI is micro-structuring of the optical lithography. At present, the lithography technique can form patterns in a size just under the light wavelength of the object lithography apparatus. For example, in the case of a 1 GB DRAM, a lithography apparatus that uses a light source of KrF excimer laser whose wavelength is 0.248 m must form word and data lines at a width of 0.16 m respectively.
In order to form a pattern in a size under the wavelength such way, super-resolution techniques such as phase shifting, off-axis illumination, etc. are used. The super-resolution technique is effective for forming and space (L&S) patterns in which simple lines such as word and data lines are formed in a memory repetitively. This is because the phase of a light passing adjacent line patterns is shifted by 180°, thereby the diffracted lights kill each other at each boundary between line patterns and a space pattern is formed there respectively. In the case of such super-resolution technique, the coherent factor is set to about 0.3, which is smaller than usual, thereby to increase mutual light interferences.
L&S patterns can be formed in a size under the wavelength using the above method. However, it is found that the method is confronted with problems when forming a pattern off the lines and spaces (L&S), for example, when forming connecting portions between a memory array and a peripheral circuit. This is because the light is diffracted at ends and corners of interconnects and the diffracted lights interfere each other, thereby a resist pattern becomes thinner than the master pattern there. And in the worst case, break failures occur in those interconnects. Hereunder, description will be made for new facts found by the present inventor, etc. through investigation with respect to the above problems.
FIG. 14 shows an explanatory view of such a new discovery. FIG. 14(a) shows a conventional masking pattern for the word lines (WL) at a boundary between a memory array and a sub-word driver (SWD) or a word shunting area of a DRAM. In the sub-word driver (SWD), each word line is expanded to form a dog bone pattern so as to secure a space for placing a contact thereon. In this example, a sub-word driver (SWD) and a memory array are disposed alternately as to be described later in detail. The word lines WL0, 3, 4, and 7 are connected to the left side sub-word driver (SWD) and the word lines WL1, 2, 5, and 6 are connected to the right side sub-word driver (SWD).
FIG. 14(b) shows a concept chart of a resist pattern obtained through a lithographic treatment performed for the pattern shown in FIG. 14(a) using a lithography apparatus on the following conditions of the light source; KrF excimer laser of a wavelength of λ=0.248 μm, numerical aperture of the lens NA=0.6, coherent factor σ=0.3, and reduction rate K=⅕. And, short failures have occurred between the ends of adjacent word lines (WL) and break failures have occurred around dog-bone portions. Those failures are caused by bad influences of light interferences.
Hereunder, this phenomenon will be described concretely through an optical simulation. In this simulation, contour lines of the light intensities obtained on a resist film are computed on the basis of the master pattern and the optical constants of the lithography apparatus. FIG. 15(a) shows a conventional masking pattern for the tips of word lines. The width and space of each word line are set to 0.16 μm. The optical constants are λ=0.248 μm, NA=0.6, σ=0.3, defocusing=−0.5 μm, and a spherical aberration is assumed. A phase-shift lithographic technique is used in this simulation. A 0°-phase is assigned to each pattern shown with right-up oblique lines and a 180°-phase is assigned to each pattern shown with right-down oblique lines. Principally, similar results can also be obtained with the off-axis illumination lithography technique. In all the subsequent simulations, the same optical conditions are assumed. A reduction projector is used for exposure in the optical lithography. In the case of light exposure at a reduction rate of K(K<1), the actual circuit pattern and the resist pattern are expanded by K times the masking pattern respectively. For example, at K=⅕, the line width of the masking pattern is 0.8 μm so as to obtain an interconnect width of 0.16 μm, but the masking pattern is reduced to the same size as those of the circuit pattern and the resist pattern for simplification thereafter. FIG. 14(b) shows the distribution of light intensities, obtained as an optical image through computation from this pattern. In other words, FIG. 14(b) shows the contour lines of the relative light intensities of 0.18, 0.32, and 0.53 respectively. The light intensity is defined as 1 for the light transmittance in an enough large pattern. The same three contour lines are indicated in all the subsequent optical simulation results.
FIG. 15(b) shows a resist pattern that can obtain a contour line actually from a light intensity of 0.32. Word lines are formed at equal pitches at places away enough from the ends of the resist pattern. However, the contour line for a light intensity of 0.18 (the outermost line in the pattern) is not separated from adjacent word lines at the tips of the lines. This indicates that the light intensity is not lowered enough at this portion due to the effect of the light interference. Consequently, the resist remains after the development, thereby causing short failures to occur between word lines at a rather high possibility.
In such a dog-bone portion, the contour line of the light intensity of 0.53 breaks. This is because the light intensity in that portion is low. Consequently, the resist will be thinned and there is a high probability that break failures will occur there in the development process.
FIG. 16(a) shows a conventional masking pattern for the tips of the second word lines. In this example, the sub-word driver (SWD) or shunting area is disposed at the left side of each corresponding memory array and all the word lines are connected to their left side sub-word driver (SWD). Even in this case, the contour line of the 0.18 light intensity (the outermost contour line in the pattern) is not separated from adjacent word lines, so there is a high probability that short failures will occur between those word lines.
Under such circumstances, it is an object of the present invention to prevent short and break failures from occurrence at the tip of each L&S pattern, etc.